Field of the Disclosure
The present invention is directed to improved chip packaging and specifically to embedded chips wherewith passive components such as capacitors and filters are incorporated within the Chip package.
Description of the Related Art
Driven by an ever greater demand for miniaturization of ever more complex electronic components, consumer electronics such as computing and telecommunication devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically insulated from each other by a dielectric material.
The general requirement for such support structures is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price.
Of the various approaches for achieving these requirements, one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate through to the previously deposited metal layer for subsequent filling with a metal, usually copper, that is deposited therein by a plating technique. This approach to creating vias is sometimes referred to as ‘drill & fill’, and the vias created thereby may be referred to as ‘drilled & filled vias’.
There are a number of disadvantages with the drilled & filled via approach. Since each via is required to be separately drilled, the throughput rate is limited, and the costs of fabricating sophisticated, multi-via IC substrates and interposers becomes prohibitive. In large arrays it is difficult to produce a high density of high quality vias having different sizes and shapes in close proximity to each other by the drill & fill methodology. Furthermore, laser drilled vias have rough sides walls and taper inwards through the thickness of the dielectric material. This tapering reduces the effective diameter of the vias. It may also adversely affect the electrical contact to the previous conductive metal layer—especially at ultra small via diameters, thereby causing reliability issues. Additionally, the side walls are particularly rough where the dielectric being drilled is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness may create additional stray inductances.
The filling process of the drilled via holes is usually achieved by copper electroplating. The electroplating deposition technique may result in dimpling, where a small crater appears at the top of the via. Alternatively, overfill may result, where a via channel is filled with more copper than it can hold, and a domed upper surface that protrudes over the surrounding material is created. Both dimpling and overfill tend to create difficulties when subsequently stacking vias one on top of the other, as required when fabricating high-density substrates and interposers. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in proximity to smaller vias within the same interconnecting layer of the interposer or IC substrate design.
While the range of acceptable sizes and reliability is improving over time, the disadvantages described hereinabove are intrinsic to the drill & fill technology and are expected to limit the range of possible via sizes. It will further be noted that laser drilling is best for creating round via channels. Although slot shaped via channels may theoretically be fabricated by laser milling, in practice, the range of geometries that may be fabricated is somewhat limited and vias in a given support structure are typically cylindrical and substantially identical.
Fabrication of vias by drill & fill is expensive and it is difficult to evenly and consistently fill the via channels created thereby with copper using the relatively, cost-effective electroplating process.
Laser drilled vias in composite dielectric materials are practically limited to diameters of 60×10−6 m (60 microns), and even so suffer from significant tapering and rough side walls due to the nature of the composite material drilled and in consequence of the ablation process involved.
In addition to the other limitations of laser drilling as described hereinabove, there is a further limitation of the drill & fill technology in that it is difficult to create different diameter vias in the same layer, since when drill different sized via channels are drilled and then filled with metal to fabricate different sized vias, the via channels fill up at different rates. Consequently, the typical problems of dimpling or overfill that characterize drill & fill technology are exasperated, since it is impossible to simultaneously optimize deposition techniques for different sized vias.
An alternative solution that overcomes many of the disadvantages of the drill & fill approach, is to fabricate vias by depositing copper or other metal into a pattern created in a photo-resist, using a technology otherwise known as ‘pattern plating’.
In pattern plating, a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern, and selectively removed to make trenches that expose the seed layer. Via posts are created by depositing Copper into the photo-resist trenches. The remaining photo-resist is then removed leaving the upstanding via posts, the seed layer is etched away, and a dielectric material, that is typically a polymer impregnated glass fiber mat, is laminated thereover and therearound to encase the vias posts. Various techniques and processes can then be used to planarize the dielectric material, removing part of it to expose the tops of the via posts to allow conductive connection to ground thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
In an alternative but closely linked technology, known hereinafter as ‘panel plating’, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on top of the substrate, and a pattern is developed therein. The pattern of developed photo-resist is stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias.
After stripping away the undeveloped photo-resist, a dielectric material, such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. After planarizing, subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
The via layers created by pattern plating or panel plating methodologies described above are typically known as ‘via posts’ and feature layers from copper.
It will be appreciated that the general thrust of the microelectronic evolution is directed towards fabricating ever smaller, thinner, lighter and more powerful products having high reliability. The use of thick cored interconnects prevents ultra-thin products being attainable. To create ever higher densities of structures in the interconnect IC substrate or ‘interposer’, ever more layers of ever smaller connections are required. Indeed, sometimes it is desirable to stack components on top of each other.
If plated laminated structures are deposited on a copper or other appropriate sacrificial substrate, the substrate may be etched away leaving free standing, coreless laminar structures. Further layers may be deposited on the side previously adhered to the sacrificial substrate, thereby enabling a two sided build up, which minimizes warping and aids the attaining of planarity.
One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or features in a dielectric matrix. The metal may be copper and the dielectric may be a fiber reinforced polymer. Typically a polymer with a high glass transition temperature (Tg) is used, such as polyimide, for example. These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd.
For example, U.S. Pat. No. 7,682,972 to Hurwitz et al. titled “Advanced multilayer coreless support structures and method for their fabrication” describes a method of fabricating a free standing membrane including a via array in a dielectric for use as a precursor in the construction of superior electronic support structures. The method includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias. This publication is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,669,320 to Hurwitz et al. titled “Coreless cavity substrates for chip packaging and their fabrication” describes a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper. This publication is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,635,641 to Hurwitz et al. titled “integrated circuit support structures and their fabrication” describes a method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second hall stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto. This publication is incorporated herein by reference in its entirety.
Over time, it is anticipated that both drill & fill technologies and via post deposition will enable fabrication of substrates with further miniaturization and higher densities of vias and features. Nevertheless, it would appear likely that developments in via post technology will maintain a competitive edge.
Substrates enable chips to interface with other components. Chips have to be bonded to substrates through assembly processes that provide reliable electronic connections to enable electronic communication between chips and substrates.
Embedding chips within the interposers to the outside world enables shrinking the chip package, shortening the connections to the outside world, offers cost savings by simpler manufacturing that eliminates die to substrate assembly processes and potentially has increased reliability.
Essentially, the concept of embedding active components such as analog, digital and MEMS chips involves the construction of chip support structures or substrates, having vias around the chip.
One way of achieving embedded chips is to fabricate chip support structures onto the chip array on the wafer where the circuitry of the support structure is larger than the die unit size. This is known as Fan Out Wafer Layer Packaging (FOWLP). Although the size of silicon wafers is growing, expensive material sets and manufacturing process are still limiting the wafer diameter size to 12″, thereby limiting the number of FOWLP units one can place on the wafer. Despite the fact that 18″ wafers are under consideration, the investment required, materials sets and equipment are still unknown. The limited number of chip support structures that may be processed at one time increases the unit cost of FOWLP, and make it too expensive for markets requiring highly competitive pricing, such as wireless communication, home appliances and automotive markets.
FOWLP also represents a performance limitation since the metal features placed over the silicon wafer as fan-out or fan-in circuitry are limited in thickness to a few microns. This creates electrical resistance challenges.
An alternative fabrication route involves sectioning the wafer to separate the chips and embedding the chips within a panel consisting of dielectric layers with copper interconnects. One advantage of this alternative route is that the panels may be very much larger with very many more chips embedded in a single process. For example, whereas for example, a 12″ wafer enables 2,500 FOWLP chips having dimensions of 5 mm×5 mm to be processed in one go, current panels used the applicant, Zhuhai Access, are 25″×21″, enabling 10,000 chips to be processed in one go. Since the price of processing such panels is significantly cheaper than on wafer processing, and since the throughput per panel is 4× higher than throughput on wafer, the unit cost can drop significantly, thereby opening new markets.
In both technologies, the line spacing and the width of the tracks used in industry are shrinking over time, with 15 micron going down to 10 microns being standard on panels and 5 microns going down to 2 microns on wafers.
The advantages of embedding are many. First level assembly costs, such as wire bonding, flip chip or SMD (Surface Mount Devices) soldering, are eliminated. The electrical performance is improved since the die and substrate are seamlessly connected within a single product. The packaged dies are thinner, giving an improved form factor, and the upper surface of the embedded die package is freed up for other uses including further space saving configurations such as those using stacked die and PoP (Package on Package) technologies.
In both FOWLP and Panel based embedded die technologies, the chips are packaged as an array (on wafer or panel), and, once fabricated, are separated by dicing.
RF (Radio Frequency) technologies, such as Wi-Fi, Bluetooth and the like, are becoming widely implemented in various devices, including mobile phones and automobiles.
In addition to Base Band processing and memory chips, RF devices in particular, require passive components such as capacitors, inductors and filters of various sorts. Such passive components may be surface mounted, but to enable ever greater miniaturization and cost savings, such devices may be embedded within the substrate.
U.S. Ser. No. 13/962,075 to Hurwitz, filed on Aug. 8, 2013, and titled “Thin Film Capacitors Embedded in Polymer Dielectric” describes a substrate comprising a capacitor consisting of metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor is embedded in a polymer based encapsulating material and may be connected to a circuit by a via post standing on said capacitor.
U.S. Ser. No. 13/962,316 filed on Aug. 8, 2013, and titled “Multilayer Structures and Embedded Features” describes a composite electronic structure comprising at least one feature layer and at least one adjacent via layer; the layers extending in an X-Y plane and having height z, wherein the structure comprises at least one capacitor coupled in series or in parallel to at least one inductor to provide at least one filter; the at least one capacitor being sandwiched between the at least one feature layer and at least one via in said at least adjacent via layer, such that the at least one via stands on the at least one capacitor, and the at least one of the first feature layer and the adjacent via layer includes at least one inductor extending in the XY plane.
U.S. Ser. No. 14/269,884 to Hurwitz, filed of May 5, 2014 and titled “Interposer Frame with Polymer Matrix and Methods of Fabrication” teaches an array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. Chips may be placed in the sockets and then held in place by a polymer based dielectric, thereby embedding the chip in the frame.